Cloud FPGA Security

When:
Friday, May 7, 2021, 11:00 am - 12:00 pm PDTiCal
Where:
Virtual via ZoomThis event is open to the public.
Type:
Heterogeneous and Non-Traditional Computing Seminar
Speaker:
Jakub Szefer, Associate Professor, Dept. of Electrical Engineering, Yale University
Video Recording:
https://usc.zoom.us/j/93379193999
Description:

Abstract: Recent introduction of FPGAs into public cloud datacenters gives users ability of to request customizable hardware resources quickly, flexibly, and on-demand. However, as public cloud providers make FPGAs available to many, potentially mutually-untrusting users, security of these FPGA deployments needs to be analyzed, and defenses developed. This talk will discuss cloud computing and FPGA security from the perspective of side and covert channel attacks that could be mounted remotely. Especially we want to address and prevent means for sensitive information, such as cryptographic keys or information about machine learning models from being leaked out. The talk will first cover our recent work on single-tenant FPGA-accelerated cloud computing and cover recently uncovered threats due to thermal temporal channels, spatial voltage-based channels, and different means for FPGA fingerprinting or FPGA co-location detection.  The talk will also present recent work considering security in multi-tenant setting, and show example of extracting input and other information from machine learning models running on remote FPGAs.  The objective of the talk is to motivate more research into security, and especially defenses, for FPGA-accelerated cloud computing given the threats we have uncovered.

Speaker Bio: Jakub Szefer’s research focuses on computer architecture and hardware security. His research encompasses secure processor architectures, cloud security, FPGA attacks and defenses, and hardware FPGA implementation of cryptographic algorithms. His research is supported through National Science Foundation and industry grants and donations. He is currently an Associate Professor of Electrical Engineering at Yale University, where he leads the Computer Architecture and Security Laboratory (CASLAB). Prior to joining Yale, he received Ph.D. and M.A. degrees in Electrical Engineering from Princeton University, and B.S. degree with highest honors in Electrical and Computer Engineering from University of Illinois at Urbana-Champaign. He has received the NSF CAREER award in 2017. Jakub is the author of first book focusing on processor architecture security: “Principles of Secure Processor Architecture Design”, published in 2018. Recently, he has been promoted to the IEEE Senior Member rank in 2019. Details of Jakub’s research can be found at: https://caslab.csl.yale.edu/~jakub

Host: Matt French <mfrench@isi.edu>

Zoom: https://usc.zoom.us/j/93379193999

Please join the zoom meeting using your @USC.EDU Zoom account if possible. If you're joining as a guest without a USC zoom account, please contact the seminar host before the meeting to register your interest. Thanks!

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